A DC to DC voltage doubler circuit is a power electronics configuration that takes a low‑voltage direct current source and produces an output voltage approximately twice the input level without using a transformer. But by storing energy in reactive components during one half of a switching cycle and releasing it in series with the input during the other half, the circuit effectively adds the input voltage to itself, yielding a doubled potential. This technique is widely employed in battery‑powered devices, RFID tags, sensor interfaces, and low‑cost power supplies where isolation is not required but a higher voltage is needed from a modest supply And that's really what it comes down to..
Working Principle of a DC to DC Voltage Doubler
At its core, a voltage doubler relies on two fundamental actions: charge pumping and series addition. During the first phase of a switching period, a capacitor is charged to the input voltage Vin through a diode or a switch. In the second phase, the charged capacitor is reconfigured so that its voltage adds to the instantaneous input voltage, appearing across the load as Vout ≈ 2·Vin. The process repeats at a high frequency, allowing the output to be smoothed by additional filtering capacitors Simple as that..
- Switching element – typically a MOSFET, BJT, or dedicated charge‑pump IC that alternates the circuit topology.
- Diodes – steer current flow to ensure the capacitor charges and discharges in the correct direction.
- Energy‑storage capacitors – hold the charge that will be added to the input voltage.
- Inductor (optional) – in some boost‑based doublers, an inductor stores energy and improves efficiency at higher power levels.
The switching frequency determines the ripple magnitude and the size of the required capacitors; higher frequencies allow smaller passive components but increase switching losses.
Types of DC‑DC Voltage Doubler Circuits
Several topologies achieve the voltage‑doubling function, each suited to different power, efficiency, and complexity requirements And that's really what it comes down to..
1. Switched‑Capacitor Charge Pump
The simplest form uses only capacitors and diodes (or MOSFET switches). A two‑phase clock drives the switches, moving charge between capacitors.
Advantages: No inductor, very low profile, easy to integrate in CMOS.
Disadvantages: Efficiency drops with load current because the output resistance of the charge pump grows; suitable for low‑power applications (< 100 mA) Worth knowing..
2. Cockcroft‑Walton Multiplier (Two‑Stage)
A cascade of diodes and capacitors where each stage adds the peak input voltage. A two‑stage Cockcroft‑Walton network is essentially a voltage doubler.
Advantages: Can achieve high voltages with modest component ratings; good for pulsed applications.
Disadvantages: High ripple and considerable voltage drop under load; requires many components for higher multiplication factors It's one of those things that adds up..
3. Boost Converter with Voltage‑Doubler Output
A standard boost converter is followed by a diode‑capacitor network that doubles the boosted voltage. The boost stage first raises the input to an intermediate level (e.g., 1.5·Vin), then the doubler adds another Vin, yielding roughly 2·Vin.
Advantages: Higher efficiency at medium power levels (up to several watts) because the boost stage handles most of the power transfer.
Disadvantages: More complex control loop; requires an inductor and a PWM controller Which is the point..
4. Charge‑Pump Integrated ICs
Many manufacturers offer dedicated voltage‑doubler charge‑pump ICs that include internal switches, timing, and protection. These are ideal for space‑constrained designs.
Advantages: Minimal external parts, built‑in soft‑start and over‑current protection.
Disadvantages: Limited to the current rating specified by the IC (often < 500 mA); cost higher than discrete implementations.
Design Steps for a Discrete Switched‑Capacitor Doubler
Designing a charge‑pump doubler involves selecting the switching frequency, capacitor values, diode ratings, and estimating output ripple.
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Define specifications
- Input voltage Vin (e.g., 3.3 V)
- Desired output voltage Vout ≈ 2·Vin (6.6 V)
- Maximum load current Iout (e.g., 50 mA)
- Allowable output ripple ΔVout (e.g., 50 mV peak‑to‑peak)
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Choose switching frequency fsw
A higher frequency reduces required capacitance but increases switching loss. For low‑power designs, 100 kHz–1 MHz is typical. Assume fsw = 500 kHz. -
Calculate the effective resistance of the charge pump
The output resistance Rout ≈ 1/(·fsw·C) for a two‑phase pump, where C is the flying capacitor value. Rearranging gives:
[ C \ge \frac{1}{R_{out} \cdot f_{sw}} ]
The desired Rout can be derived from the allowable voltage drop at full load:
[ R_{out} = \frac{V_{in} - V_{out}/2}{I_{out}} ]
For a 3.3 V input aiming for 6.6 V output, the ideal drop is zero; practically we allow 0.2 V drop:
[ R_{out} = \frac{0.2\text{ V}}{0.05\text{ A}} = 4\ \Omega ]
Thus:
[ C \ge \frac{1}{4\ \Omega \times 5\times10^{5}\text{ Hz}} = 5\ \text{nF} ]
Choose a standard value with margin, e.g., C = 22 nF (X7R ceramic) for each flying capacitor. -
Select output filter capacitor
Select output filter capacitor
The total capacitance that sees the ripple is the sum of the output filter capacitor (C_{\text{filt}}) plus the effective capacitance contributed by the charge‑pump’s flying caps. For a given ripple tolerance (\Delta V_{\text{out}}), the smallest feasible value follows from the classic approximation
[ \Delta V_{\text{out}} \approx \frac{f_{\text{sw}}}{8,C_{\text{tot}}},V_{\text{out}}, ]
where (f_{\text{sw}}) is the switch frequency and (V_{\text{out}}=2V_{\text{in}}). Solving for (C_{\text{tot}}) yields
[ C_{\text{tot}} \ge \frac{f_{\text{sw}}}{8,\Delta V_{\text{out}}},V_{\text{out}}. ]
Plugging in the example numbers ((f_{\text{sw}}=5\times10^{5},\text{Hz}), (\Delta V_{\text{out}}=50;\text{mV}), (V_{\text{out}}=6.6;\text{V})) gives
[ C_{\text{tot}} \gtrsim \frac{5\times10^{5}}{8\times5\times10^{-4}}\times6.6 \approx 41\ \mu\text{F}. ]
Because part of this capacitance resides inside the charge‑pump (each flying capacitor contributes roughly half its value to the overall loop), it is prudent to allocate a larger portion directly to (C_{\text{filt}}). A common practice is to pick (C_{\text{filt}}) around 15–25 µF (multi‑layer ceramic or tantalum) while sizing the flying caps at 22 nF as previously determined. This combination typically meets the ripple target while keeping the total capacitance modest enough to limit component count and board area Most people skip this — try not to. Still holds up..
Capacitor placement and layout
The output filter should be placed as close as possible to the charge‑pump’s completion node to minimise inductive loops and ESR contributions. On a multilayer board, a ground plane beneath the filtering network helps suppress high‑frequency noise. Additionally, placing a small series resistor (≈ 10 Ω) between the fly‑capacitors and the filter can damp resonant peaks caused by parasitic inductance Easy to understand, harder to ignore. Practical, not theoretical..
Thermal and reliability considerations
Charge‑pump doublers operate with very low quiescent current, so self‑heating is minimal. Still, the diodes used in the classic “diode‑capacitor” version still dissipate a fraction of the input power. Selecting Schottky diodes with a low forward drop (≈ 0.2 V) further reduces heat generation. If the ambient temperature exceeds 70 °C, incorporating a small heatsink or allowing airflow can become necessary for continuous high‑load operation.
Comparison with integrated solutions
While dedicated ICs provide soft‑start, built‑in over‑current and short‑circuit protection, they also lock you into their maximum current rating (typically below 500 mA for a single die). In contrast, a discrete implementation can be scaled linearly with the number of pump stages—adding more phases simply multiplies the voltage gain without sacrificing efficiency beyond a certain point. On top of that, the flexible topology allows designers to fine‑tune ripple, adjust duty cycles, and integrate additional features such as programmable frequency or adaptive dead‑time compensation That's the part that actually makes a difference..
Summary of the design workflow
- Define the target input, output voltage, current, and ripple.
- Choose a suitable switching frequency that balances loss and size.
- Compute the minimum total capacitance needed to meet the ripple specification, then split it between the charge‑pump flying caps and the external filter.
- Size each flying capacitor according to the allowed output resistance (derived from the permitted voltage drop at full load).
- Select an output filter capacitor large enough to keep ripple within the budget while respecting board real‑estate constraints.
- Verify the complete loop with SPICE or a circuit simulator, paying attention to component tolerances and parasitics.
Conclusion
A discrete charge‑pump voltage doubler offers a straightforward path to double a supply when space, integration limits, or customizable performance are critical. By carefully calculating the flying‑capacitor size, adding an appropriately sized output
By carefully calculating the flying-capacitor size, adding an appropriately sized output filter, and respecting layout best practices, designers can achieve low ripple, minimal EMI, and solid operation. On top of that, the discrete approach shines in applications demanding voltage scaling beyond standard IC limits, where cost-sensitive solutions benefit from component-level optimization, or where unique requirements—such as non-standard input ranges, variable frequency operation, or custom protection schemes—cannot be met by off-the-shelf parts. In the long run, a well-executed charge-pump doubler combines simplicity with adaptability, making it a compelling choice for compact, high-efficiency power-conversion tasks where flexibility is key Simple, but easy to overlook..
Final thoughts
While integrated solutions offer convenience, the discrete charge-pump topology remains a powerful tool for engineers who need to push performance boundaries or deal with unconventional design constraints. By mastering the interplay of capacitance, switching dynamics, and noise suppression, designers can craft a voltage doubler that not only meets specifications but also thrives in demanding environments. Whether powering low-noise analog circuits, managing battery voltages in portable devices, or enabling voltage scaling in space-constrained systems, this classic topology proves its enduring value through both elegance and practicality.
